Technologies for in-processor workload phase detection

ABSTRACT

Technologies for providing in-processor workload phase detection include a sled having a compute engine, which itself includes a performance monitor unit. The compute engine obtains telemetry data from the performance monitor unit. The performance monitor unit produces telemetry data indicative of performance metrics of the sled during execution of one or more workloads. The telemetry data is indicative of a resource utilization and workload performance by the sled as the workloads are executed. The compute engine determines, from a lookup table indicative of resource utilization phases, a resource utilization phase based on the obtained telemetry data. A workload fingerprint is updated based on the determined resource utilization phase, and the workload fingerprint is output. Other embodiments are also described and claimed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Provisional PatentApplication No. 201741030632, filed Aug. 30, 2017 and U.S. ProvisionalPatent Application No. 62/584,401, filed Nov. 10, 2017.

BACKGROUND

In systems that distribute workloads among multiple compute devices(e.g., in a data center), a centralized server may compose nodes ofcompute devices to process the workloads. Each node represents a logicalaggregation of resources (e.g., compute, storage, acceleration, and thelike) provided by each compute device. In such a system, the centralizedserver may monitor resource utilization in each node and underlyingcompute device, which allows the centralized server to adjust theallocation of resources for a workload given the reported resourceutilization in the compute devices. Typically, doing so involves eachcomputing device collecting resource utilization metrics and reporting,through a network, the collected metrics to the centralized server,which in turn analyzes the metrics to identify a corresponding phase ofthe workload being executed. Based on the phase, the centralized serverperforms some action based on the analysis (e.g., adjusting resources ina compute device, assigning a portion of a workload to another computedevice, etc.). Such an approach may consume a considerable amount ofnetwork resources in the system.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. Where considered appropriate, referencelabels have been repeated among the figures to indicate corresponding oranalogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a datacenter for executing workloads with disaggregated resources;

FIG. 2 is a simplified diagram of at least one embodiment of a pod ofthe data center of FIG. 1;

FIG. 3 is a perspective view of at least one embodiment of a rack thatmay be included in the pod of FIG. 2;

FIG. 4 is a side plan elevation view of the rack of FIG. 3;

FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mountedtherein;

FIG. 6 is a is a simplified block diagram of at least one embodiment ofa top side of the sled of FIG. 5;

FIG. 7 is a simplified block diagram of at least one embodiment of abottom side of the sled of FIG. 6;

FIG. 8 is a simplified block diagram of at least one embodiment of acompute sled usable in the data center of FIG. 1;

FIG. 9 is a top perspective view of at least one embodiment of thecompute sled of FIG. 8;

FIG. 10 is a simplified block diagram of at least one embodiment of anaccelerator sled usable in the data center of FIG. 1;

FIG. 11 is a top perspective view of at least one embodiment of theaccelerator sled of FIG. 10;

FIG. 12 is a simplified block diagram of at least one embodiment of astorage sled usable in the data center of FIG. 1;

FIG. 13 is a top perspective view of at least one embodiment of thestorage sled of FIG. 12;

FIG. 14 is a simplified block diagram of at least one embodiment of amemory sled usable in the data center of FIG. 1; and

FIG. 15 is a simplified block diagram of a system that may beestablished within the data center of FIG. 1 to execute workloads withmanaged nodes composed of disaggregated resources.

FIG. 16 is a simplified block diagram of at least one embodiment of asystem for performing in-processor workload phase detection;

FIG. 17 is a simplified block diagram of at least one embodiment of acompute sled of the system of FIG. 16;

FIG. 18 is a simplified block diagram of at least one embodiment of anenvironment that may be established by the compute sled of FIGS. 16 and17; and

FIGS. 19-21 are a simplified flow diagram of at least one embodiment ofa method for detecting workload phases via a processor of the computesled of FIGS. 16 and 17.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and will be describedherein in detail. It should be understood, however, that there is nointent to limit the concepts of the present disclosure to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives consistent with the presentdisclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,”“an illustrative embodiment,” etc., indicate that the embodimentdescribed may include a particular feature, structure, orcharacteristic, but every embodiment may or may not necessarily includethat particular feature, structure, or characteristic. Moreover, suchphrases are not necessarily referring to the same embodiment. Further,when a particular feature, structure, or characteristic is described inconnection with an embodiment, it is submitted that it is within theknowledge of one skilled in the art to effect such feature, structure,or characteristic in connection with other embodiments whether or notexplicitly described. Additionally, it should be appreciated that itemsincluded in a list in the form of “at least one A, B, and C” can mean(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).Similarly, items listed in the form of “at least one of A, B, or C” canmean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, inhardware, firmware, software, or any combination thereof. The disclosedembodiments may also be implemented as instructions carried by or storedon a transitory or non-transitory machine-readable (e.g.,computer-readable) storage medium, which may be read and executed by oneor more processors. A machine-readable storage medium may be embodied asany storage device, mechanism, or other physical structure for storingor transmitting information in a form readable by a machine (e.g., avolatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown inspecific arrangements and/or orderings. However, it should beappreciated that such specific arrangements and/or orderings may not berequired. Rather, in some embodiments, such features may be arranged ina different manner and/or order than shown in the illustrative figures.Additionally, the inclusion of a structural or method feature in aparticular figure is not meant to imply that such feature is required inall embodiments and, in some embodiments, may not be included or may becombined with other features.

Referring now to FIG. 1, a data center 100 in which disaggregatedresources may cooperatively execute one or more workloads (e.g.,applications on behalf of customers) includes multiple pods 110, 120,130, 140, each of which includes one or more rows of racks. As describedin more detail herein, each rack houses multiple sleds, which each maybe embodied as a compute device, such as a server, that is primarilyequipped with a particular type of resource (e.g., memory devices, datastorage devices, accelerator devices, general purpose processors). Inthe illustrative embodiment, the sleds in each pod 110, 120, 130, 140are connected to multiple pod switches (e.g., switches that route datacommunications to and from sleds within the pod). The pod switches, inturn, connect with spine switches 150 that switch communications amongpods (e.g., the pods 110, 120, 130, 140) in the data center 100. In someembodiments, the sleds may be connected with a fabric using IntelOmni-Path technology. As described in more detail herein, resourceswithin sleds in the data center 100 may be allocated to a group(referred to herein as a “managed node”) containing resources from oneor more other sleds to be collectively utilized in the execution of aworkload. The workload can execute as if the resources belonging to themanaged node were located on the same sled. The resources in a managednode may even belong to sleds belonging to different racks, and even todifferent pods 110, 120, 130, 140. Some resources of a single sled maybe allocated to one managed node while other resources of the same sledare allocated to a different managed node (e.g., one processor assignedto one managed node and another processor of the same sled assigned to adifferent managed node). By disaggregating resources to sleds comprisedpredominantly of a single type of resource (e.g., compute sledscomprising primarily compute resources, memory sleds containingprimarily memory resources), and selectively allocating and deallocatingthe disaggregated resources to form a managed node assigned to execute aworkload, the data center 100 provides more efficient resource usageover typical data centers comprised of hyperconverged servers containingcompute, memory, storage and perhaps additional resources). As such, thedata center 100 may provide greater performance (e.g., throughput,operations per second, latency, etc.) than a typical data center thathas the same number of resources.

Referring now to FIG. 2, the pod 110, in the illustrative embodiment,includes a set of rows 200, 210, 220, 230 of racks 240. Each rack 240may house multiple sleds (e.g., sixteen sleds) and provide power anddata connections to the housed sleds, as described in more detailherein. In the illustrative embodiment, the racks in each row 200, 210,220, 230 are connected to multiple pod switches 250, 260. The pod switch250 includes a set of ports 252 to which the sleds of the racks of thepod 110 are connected and another set of ports 254 that connect the pod110 to the spine switches 150 to provide connectivity to other pods inthe data center 100. Similarly, the pod switch 260 includes a set ofports 262 to which the sleds of the racks of the pod 110 are connectedand a set of ports 264 that connect the pod 110 to the spine switches150. As such, the use of the pair of switches 250, 260 provides anamount of redundancy to the pod 110. For example, if either of theswitches 250, 260 fails, the sleds in the pod 110 may still maintaindata communication with the remainder of the data center 100 (e.g.,sleds of other pods) through the other switch 250, 260. Furthermore, inthe illustrative embodiment, the switches 150, 250, 260 may be embodiedas dual-mode optical switches, capable of routing both Ethernet protocolcommunications carrying Internet Protocol (IP) packets andcommunications according to a second, high-performance link-layerprotocol (e.g., Intel's Omni-Path Architecture's, Infiniband) viaoptical signaling media of an optical fabric.

It should be appreciated that each of the other pods 120, 130, 140 (aswell as any additional pods of the data center 100) may be similarlystructured as, and have components similar to, the pod 110 shown in anddescribed in regard to FIG. 2 (e.g., each pod may have rows of rackshousing multiple sleds as described above). Additionally, while two podswitches 250, 260 are shown, it should be understood that in otherembodiments, each pod 110, 120, 130, 140 may be connected to differentnumber of pod switches (e.g., providing even more failover capacity).

Referring now to FIGS. 3-5, each illustrative rack 240 of the datacenter 100 includes two elongated support posts 302, 304, which arearranged vertically. For example, the elongated support posts 302, 304may extend upwardly from a floor of the data center 100 when deployed.The rack 240 also includes one or more horizontal pairs 310 of elongatedsupport arms 312 (identified in FIG. 3 via a dashed ellipse) configuredto support a sled of the data center 100 as discussed below. Oneelongated support arm 312 of the pair of elongated support arms 312extends outwardly from the elongated support post 302 and the otherelongated support arm 312 extends outwardly from the elongated supportpost 304.

In the illustrative embodiments, each sled of the data center 100 isembodied as a chassis-less sled. That is, each sled has a chassis-lesscircuit board substrate on which physical resources (e.g., processors,memory, accelerators, storage, etc.) are mounted as discussed in moredetail below. As such, the rack 240 is configured to receive thechassis-less sleds. For example, each pair 310 of elongated support arms312 defines a sled slot 320 of the rack 240, which is configured toreceive a corresponding chassis-less sled. To do so, each illustrativeelongated support arm 312 includes a circuit board guide 330 configuredto receive the chassis-less circuit board substrate of the sled. Eachcircuit board guide 330 is secured to, or otherwise mounted to, a topside 332 of the corresponding elongated support arm 312. For example, inthe illustrative embodiment, each circuit board guide 330 is mounted ata distal end of the corresponding elongated support arm 312 relative tothe corresponding elongated support post 302, 304. For clarity of theFigures, not every circuit board guide 330 may be referenced in eachFigure.

Each circuit board guide 330 includes an inner wall that defines acircuit board slot 380 configured to receive the chassis-less circuitboard substrate of a sled 400 when the sled 400 is received in thecorresponding sled slot 320 of the rack 240. To do so, as shown in FIG.4, a user (or robot) aligns the chassis-less circuit board substrate ofan illustrative chassis-less sled 400 to a sled slot 320. The user, orrobot, may then slide the chassis-less circuit board substrate forwardinto the sled slot 320 such that each side edge 414 of the chassis-lesscircuit board substrate is received in a corresponding circuit boardslot 380 of the circuit board guides 330 of the pair 310 of elongatedsupport arms 312 that define the corresponding sled slot 320 as shown inFIG. 4. By having robotically accessible and robotically manipulablesleds comprising disaggregated resources, each type of resource can beupgraded independently of each other and at their own optimized refreshrate. Furthermore, the sleds are configured to blindly mate with powerand data communication cables in each rack 240, enhancing their abilityto be quickly removed, upgraded, reinstalled, and/or replaced. As such,in some embodiments, the data center 100 may operate (e.g., executeworkloads, undergo maintenance and/or upgrades, etc.) without humaninvolvement on the data center floor. In other embodiments, a human mayfacilitate one or more maintenance or upgrade operations in the datacenter 100.

It should be appreciated that each circuit board guide 330 is dualsided. That is, each circuit board guide 330 includes an inner wall thatdefines a circuit board slot 380 on each side of the circuit board guide330. In this way, each circuit board guide 330 can support achassis-less circuit board substrate on either side. As such, a singleadditional elongated support post may be added to the rack 240 to turnthe rack 240 into a two-rack solution that can hold twice as many sledslots 320 as shown in FIG. 3. The illustrative rack 240 includes sevenpairs 310 of elongated support arms 312 that define a correspondingseven sled slots 320, each configured to receive and support acorresponding sled 400 as discussed above. Of course, in otherembodiments, the rack 240 may include additional or fewer pairs 310 ofelongated support arms 312 (i.e., additional or fewer sled slots 320).It should be appreciated that because the sled 400 is chassis-less, thesled 400 may have an overall height that is different than typicalservers. As such, in some embodiments, the height of each sled slot 320may be shorter than the height of a typical server (e.g., shorter than asingle rank unit, “1U”). That is, the vertical distance between eachpair 310 of elongated support arms 312 may be less than a standard rackunit “1U.” Additionally, due to the relative decrease in height of thesled slots 320, the overall height of the rack 240 in some embodimentsmay be shorter than the height of traditional rack enclosures. Forexample, in some embodiments, each of the elongated support posts 302,304 may have a length of six feet or less. Again, in other embodiments,the rack 240 may have different dimensions. Further, it should beappreciated that the rack 240 does not include any walls, enclosures, orthe like. Rather, the rack 240 is an enclosure-less rack that is openedto the local environment. Of course, in some cases, an end plate may beattached to one of the elongated support posts 302, 304 in thosesituations in which the rack 240 forms an end-of-row rack in the datacenter 100.

In some embodiments, various interconnects may be routed upwardly ordownwardly through the elongated support posts 302, 304. To facilitatesuch routing, each elongated support post 302, 304 includes an innerwall that defines an inner chamber in which the interconnect may belocated. The interconnects routed through the elongated support posts302, 304 may be embodied as any type of interconnects including, but notlimited to, data or communication interconnects to provide communicationconnections to each sled slot 320, power interconnects to provide powerto each sled slot 320, and/or other types of interconnects.

The rack 240, in the illustrative embodiment, includes a supportplatform on which a corresponding optical data connector (not shown) ismounted. Each optical data connector is associated with a correspondingsled slot 320 and is configured to mate with an optical data connectorof a corresponding sled 400 when the sled 400 is received in thecorresponding sled slot 320. In some embodiments, optical connectionsbetween components (e.g., sleds, racks, and switches) in the data center100 are made with a blind mate optical connection. For example, a dooron each cable may prevent dust from contaminating the fiber inside thecable. In the process of connecting to a blind mate optical connectormechanism, the door is pushed open when the end of the cable enters theconnector mechanism. Subsequently, the optical fiber inside the cableenters a gel within the connector mechanism and the optical fiber of onecable comes into contact with the optical fiber of another cable withinthe gel inside the connector mechanism.

The illustrative rack 240 also includes a fan array 370 coupled to thecross-support arms of the rack 240. The fan array 370 includes one ormore rows of cooling fans 372, which are aligned in a horizontal linebetween the elongated support posts 302, 304. In the illustrativeembodiment, the fan array 370 includes a row of cooling fans 372 foreach sled slot 320 of the rack 240. As discussed above, each sled 400does not include any on-board cooling system in the illustrativeembodiment and, as such, the fan array 370 provides cooling for eachsled 400 received in the rack 240. Each rack 240, in the illustrativeembodiment, also includes a power supply associated with each sled slot320. Each power supply is secured to one of the elongated support arms312 of the pair 310 of elongated support arms 312 that define thecorresponding sled slot 320. For example, the rack 240 may include apower supply coupled or secured to each elongated support arm 312extending from the elongated support post 302. Each power supplyincludes a power connector configured to mate with a power connector ofthe sled 400 when the sled 400 is received in the corresponding sledslot 320. In the illustrative embodiment, the sled 400 does not includeany on-board power supply and, as such, the power supplies provided inthe rack 240 supply power to corresponding sleds 400 when mounted to therack 240.

Referring now to FIG. 6, the sled 400, in the illustrative embodiment,is configured to be mounted in a corresponding rack 240 of the datacenter 100 as discussed above. In some embodiments, each sled 400 may beoptimized or otherwise configured for performing particular tasks, suchas compute tasks, acceleration tasks, data storage tasks, etc. Forexample, the sled 400 may be embodied as a compute sled 800 as discussedbelow in regard to FIGS. 8-9, an accelerator sled 1000 as discussedbelow in regard to FIGS. 10-11, a storage sled 1200 as discussed belowin regard to FIGS. 12-13, or as a sled optimized or otherwise configuredto perform other specialized tasks, such as a memory sled 1400,discussed below in regard to FIG. 14.

As discussed above, the illustrative sled 400 includes a chassis-lesscircuit board substrate 602, which supports various physical resources(e.g., electrical components) mounted thereon. It should be appreciatedthat the circuit board substrate 602 is “chassis-less” in that the sled400 does not include a housing or enclosure. Rather, the chassis-lesscircuit board substrate 602 is open to the local environment. Thechassis-less circuit board substrate 602 may be formed from any materialcapable of supporting the various electrical components mounted thereon.For example, in an illustrative embodiment, the chassis-less circuitboard substrate 602 is formed from an FR-4 glass-reinforced epoxylaminate material. Of course, other materials may be used to form thechassis-less circuit board substrate 602 in other embodiments.

As discussed in more detail below, the chassis-less circuit boardsubstrate 602 includes multiple features that improve the thermalcooling characteristics of the various electrical components mounted onthe chassis-less circuit board substrate 602. As discussed, thechassis-less circuit board substrate 602 does not include a housing orenclosure, which may improve the airflow over the electrical componentsof the sled 400 by reducing those structures that may inhibit air flow.For example, because the chassis-less circuit board substrate 602 is notpositioned in an individual housing or enclosure, there is no backplane(e.g., a backplate of the chassis) to the chassis-less circuit boardsubstrate 602, which could inhibit air flow across the electricalcomponents. Additionally, the chassis-less circuit board substrate 602has a geometric shape configured to reduce the length of the airflowpath across the electrical components mounted to the chassis-lesscircuit board substrate 602. For example, the illustrative chassis-lesscircuit board substrate 602 has a width 604 that is greater than a depth606 of the chassis-less circuit board substrate 602. In one particularembodiment, for example, the chassis-less circuit board substrate 602has a width of about 21 inches and a depth of about 9 inches, comparedto a typical server that has a width of about 17 inches and a depth ofabout 39 inches. As such, an airflow path 608 that extends from a frontedge 610 of the chassis-less circuit board substrate 602 toward a rearedge 612 has a shorter distance relative to typical servers, which mayimprove the thermal cooling characteristics of the sled 400.Furthermore, although not illustrated in FIG. 6, the various physicalresources mounted to the chassis-less circuit board substrate 602 aremounted in corresponding locations such that no two substantivelyheat-producing electrical components shadow each other as discussed inmore detail below. That is, no two electrical components, which produceappreciable heat during operation (i.e., greater than a nominal heatsufficient enough to adversely impact the cooling of another electricalcomponent), are mounted to the chassis-less circuit board substrate 602linearly in-line with each other along the direction of the airflow path608 (i.e., along a direction extending from the front edge 610 towardthe rear edge 612 of the chassis-less circuit board substrate 602).

As discussed above, the illustrative sled 400 includes one or morephysical resources 620 mounted to a top side 650 of the chassis-lesscircuit board substrate 602. Although two physical resources 620 areshown in FIG. 6, it should be appreciated that the sled 400 may includeone, two, or more physical resources 620 in other embodiments. Thephysical resources 620 may be embodied as any type of processor,controller, or other compute circuit capable of performing various taskssuch as compute functions and/or controlling the functions of the sled400 depending on, for example, the type or intended functionality of thesled 400. For example, as discussed in more detail below, the physicalresources 620 may be embodied as high-performance processors inembodiments in which the sled 400 is embodied as a compute sled, asaccelerator co-processors or circuits in embodiments in which the sled400 is embodied as an accelerator sled, storage controllers inembodiments in which the sled 400 is embodied as a storage sled, or aset of memory devices in embodiments in which the sled 400 is embodiedas a memory sled.

The sled 400 also includes one or more additional physical resources 630mounted to the top side 650 of the chassis-less circuit board substrate602. In the illustrative embodiment, the additional physical resourcesinclude a network interface controller (NIC) as discussed in more detailbelow. Of course, depending on the type and functionality of the sled400, the physical resources 630 may include additional or otherelectrical components, circuits, and/or devices in other embodiments.

The physical resources 620 are communicatively coupled to the physicalresources 630 via an input/output (I/O) subsystem 622. The I/O subsystem622 may be embodied as circuitry and/or components to facilitateinput/output operations with the physical resources 620, the physicalresources 630, and/or other components of the sled 400. For example, theI/O subsystem 622 may be embodied as, or otherwise include, memorycontroller hubs, input/output control hubs, integrated sensor hubs,firmware devices, communication links (e.g., point-to-point links, buslinks, wires, cables, light guides, printed circuit board traces, etc.),and/or other components and subsystems to facilitate the input/outputoperations. In the illustrative embodiment, the I/O subsystem 622 isembodied as, or otherwise includes, a double data rate 4 (DDR4) data busor a DDR5 data bus.

In some embodiments, the sled 400 may also include aresource-to-resource interconnect 624. The resource-to-resourceinterconnect 624 may be embodied as any type of communicationinterconnect capable of facilitating resource-to-resourcecommunications. In the illustrative embodiment, the resource-to-resourceinterconnect 624 is embodied as a high-speed point-to-point interconnect(e.g., faster than the I/O subsystem 622). For example, theresource-to-resource interconnect 624 may be embodied as a QuickPathInterconnect (QPI), an UltraPath Interconnect (UPI), or other high-speedpoint-to-point interconnect dedicated to resource-to-resourcecommunications.

The sled 400 also includes a power connector 640 configured to mate witha corresponding power connector of the rack 240 when the sled 400 ismounted in the corresponding rack 240. The sled 400 receives power froma power supply of the rack 240 via the power connector 640 to supplypower to the various electrical components of the sled 400. That is, thesled 400 does not include any local power supply (i.e., an on-boardpower supply) to provide power to the electrical components of the sled400. The exclusion of a local or on-board power supply facilitates thereduction in the overall footprint of the chassis-less circuit boardsubstrate 602, which may increase the thermal cooling characteristics ofthe various electrical components mounted on the chassis-less circuitboard substrate 602 as discussed above. In some embodiments, power isprovided to the processors 820 through vias directly under theprocessors 820 (e.g., through the bottom side 750 of the chassis-lesscircuit board substrate 602), providing an increased thermal budget,additional current and/or voltage, and better voltage control overtypical boards.

In some embodiments, the sled 400 may also include mounting features 642configured to mate with a mounting arm, or other structure, of a robotto facilitate the placement of the sled 600 in a rack 240 by the robot.The mounting features 642 may be embodied as any type of physicalstructures that allow the robot to grasp the sled 400 without damagingthe chassis-less circuit board substrate 602 or the electricalcomponents mounted thereto. For example, in some embodiments, themounting features 642 may be embodied as non-conductive pads attached tothe chassis-less circuit board substrate 602. In other embodiments, themounting features may be embodied as brackets, braces, or other similarstructures attached to the chassis-less circuit board substrate 602. Theparticular number, shape, size, and/or make-up of the mounting feature642 may depend on the design of the robot configured to manage the sled400.

Referring now to FIG. 7, in addition to the physical resources 630mounted on the top side 650 of the chassis-less circuit board substrate602, the sled 400 also includes one or more memory devices 720 mountedto a bottom side 750 of the chassis-less circuit board substrate 602.That is, the chassis-less circuit board substrate 602 is embodied as adouble-sided circuit board. The physical resources 620 arecommunicatively coupled to the memory devices 720 via the I/O subsystem622. For example, the physical resources 620 and the memory devices 720may be communicatively coupled by one or more vias extending through thechassis-less circuit board substrate 602. Each physical resource 620 maybe communicatively coupled to a different set of one or more memorydevices 720 in some embodiments. Alternatively, in other embodiments,each physical resource 620 may be communicatively coupled to each memorydevices 720.

The memory devices 720 may be embodied as any type of memory devicecapable of storing data for the physical resources 620 during operationof the sled 400, such as any type of volatile (e.g., dynamic randomaccess memory (DRAM), etc.) or non-volatile memory. Volatile memory maybe a storage medium that requires power to maintain the state of datastored by the medium. Non-limiting examples of volatile memory mayinclude various types of random access memory (RAM), such as dynamicrandom access memory (DRAM) or static random access memory (SRAM). Oneparticular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include next-generation nonvolatile devices, such as Intel 3DXPoint™ memory or other byte addressable write-in-place nonvolatilememory devices. In one embodiment, the memory device may be or mayinclude memory devices that use chalcogenide glass, multi-thresholdlevel NAND flash memory, NOR flash memory, single or multi-level PhaseChange Memory (PCM), a resistive memory, nanowire memory, ferroelectrictransistor random access memory (FeTRAM), anti-ferroelectric memory,magnetoresistive random access memory (MRAM) memory that incorporatesmemristor technology, resistive memory including the metal oxide base,the oxygen vacancy base and the conductive bridge Random Access Memory(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magneticjunction memory based device, a magnetic tunneling junction (MTJ) baseddevice, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, athyristor based memory device, or a combination of any of the above, orother memory. The memory device may refer to the die itself and/or to apackaged memory product. In some embodiments, the memory device maycomprise a transistor-less stackable cross point architecture in whichmemory cells sit at the intersection of word lines and bit lines and areindividually addressable and in which bit storage is based on a changein bulk resistance.

Referring now to FIG. 8, in some embodiments, the sled 400 may beembodied as a compute sled 800. The compute sled 800 is optimized, orotherwise configured, to perform compute tasks. Of course, as discussedabove, the compute sled 800 may rely on other sleds, such asacceleration sleds and/or storage sleds, to perform such compute tasks.The compute sled 800 includes various physical resources (e.g.,electrical components) similar to the physical resources of the sled400, which have been identified in FIG. 8 using the same referencenumbers. The description of such components provided above in regard toFIGS. 6 and 7 applies to the corresponding components of the computesled 800 and is not repeated herein for clarity of the description ofthe compute sled 800.

In the illustrative compute sled 800, the physical resources 620 areembodied as processors 820. Although only two processors 820 are shownin FIG. 8, it should be appreciated that the compute sled 800 mayinclude additional processors 820 in other embodiments. Illustratively,the processors 820 are embodied as high-performance processors 820 andmay be configured to operate at a relatively high power rating. Althoughthe processors 820 generate additional heat operating at power ratingsgreater than typical processors (which operate at around 155-230 W), theenhanced thermal cooling characteristics of the chassis-less circuitboard substrate 602 discussed above facilitate the higher poweroperation. For example, in the illustrative embodiment, the processors820 are configured to operate at a power rating of at least 250 W. Insome embodiments, the processors 820 may be configured to operate at apower rating of at least 350 W.

In some embodiments, the compute sled 800 may also include aprocessor-to-processor interconnect 842. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the processor-to-processor interconnect 842 may be embodied as any typeof communication interconnect capable of facilitatingprocessor-to-processor interconnect 842 communications. In theillustrative embodiment, the processor-to-processor interconnect 842 isembodied as a high-speed point-to-point interconnect (e.g., faster thanthe I/O subsystem 622). For example, the processor-to-processorinterconnect 842 may be embodied as a QuickPath Interconnect (QPI), anUltraPath Interconnect (UPI), or other high-speed point-to-pointinterconnect dedicated to processor-to-processor communications.

The compute sled 800 also includes a communication circuit 830. Theillustrative communication circuit 830 includes a network interfacecontroller (NIC) 832, which may also be referred to as a host fabricinterface (HFI). The NIC 832 may be embodied as, or otherwise include,any type of integrated circuit, discrete circuits, controller chips,chipsets, add-in-boards, daughtercards, network interface cards, otherdevices that may be used by the compute sled 800 to connect with anothercompute device (e.g., with other sleds 400). In some embodiments, theNIC 832 may be embodied as part of a system-on-a-chip (SoC) thatincludes one or more processors, or included on a multichip package thatalso contains one or more processors. In some embodiments, the NIC 832may include a local processor (not shown) and/or a local memory (notshown) that are both local to the NIC 832. In such embodiments, thelocal processor of the NIC 832 may be capable of performing one or moreof the functions of the processors 820. Additionally or alternatively,in such embodiments, the local memory of the NIC 832 may be integratedinto one or more components of the compute sled at the board level,socket level, chip level, and/or other levels.

The communication circuit 830 is communicatively coupled to an opticaldata connector 834. The optical data connector 834 is configured to matewith a corresponding optical data connector of the rack 240 when thecompute sled 800 is mounted in the rack 240. Illustratively, the opticaldata connector 834 includes a plurality of optical fibers which leadfrom a mating surface of the optical data connector 834 to an opticaltransceiver 836. The optical transceiver 836 is configured to convertincoming optical signals from the rack-side optical data connector toelectrical signals and to convert electrical signals to outgoing opticalsignals to the rack-side optical data connector. Although shown asforming part of the optical data connector 834 in the illustrativeembodiment, the optical transceiver 836 may form a portion of thecommunication circuit 830 in other embodiments.

In some embodiments, the compute sled 800 may also include an expansionconnector 840. In such embodiments, the expansion connector 840 isconfigured to mate with a corresponding connector of an expansionchassis-less circuit board substrate to provide additional physicalresources to the compute sled 800. The additional physical resources maybe used, for example, by the processors 820 during operation of thecompute sled 800. The expansion chassis-less circuit board substrate maybe substantially similar to the chassis-less circuit board substrate 602discussed above and may include various electrical components mountedthereto. The particular electrical components mounted to the expansionchassis-less circuit board substrate may depend on the intendedfunctionality of the expansion chassis-less circuit board substrate. Forexample, the expansion chassis-less circuit board substrate may provideadditional compute resources, memory resources, and/or storageresources. As such, the additional physical resources of the expansionchassis-less circuit board substrate may include, but is not limited to,processors, memory devices, storage devices, and/or accelerator circuitsincluding, for example, field programmable gate arrays (FPGA),application-specific integrated circuits (ASICs), securityco-processors, graphics processing units (GPUs), machine learningcircuits, or other specialized processors, controllers, devices, and/orcircuits.

Referring now to FIG. 9, an illustrative embodiment of the compute sled800 is shown. As shown, the processors 820, communication circuit 830,and optical data connector 834 are mounted to the top side 650 of thechassis-less circuit board substrate 602. Any suitable attachment ormounting technology may be used to mount the physical resources of thecompute sled 800 to the chassis-less circuit board substrate 602. Forexample, the various physical resources may be mounted in correspondingsockets (e.g., a processor socket), holders, or brackets. In some cases,some of the electrical components may be directly mounted to thechassis-less circuit board substrate 602 via soldering or similartechniques.

As discussed above, the individual processors 820 and communicationcircuit 830 are mounted to the top side 650 of the chassis-less circuitboard substrate 602 such that no two heat-producing, electricalcomponents shadow each other. In the illustrative embodiment, theprocessors 820 and communication circuit 830 are mounted incorresponding locations on the top side 650 of the chassis-less circuitboard substrate 602 such that no two of those physical resources arelinearly in-line with others along the direction of the airflow path608. It should be appreciated that, although the optical data connector834 is in-line with the communication circuit 830, the optical dataconnector 834 produces no or nominal heat during operation.

The memory devices 720 of the compute sled 800 are mounted to the bottomside 750 of the of the chassis-less circuit board substrate 602 asdiscussed above in regard to the sled 400. Although mounted to thebottom side 750, the memory devices 720 are communicatively coupled tothe processors 820 located on the top side 650 via the I/O subsystem622. Because the chassis-less circuit board substrate 602 is embodied asa double-sided circuit board, the memory devices 720 and the processors820 may be communicatively coupled by one or more vias, connectors, orother mechanisms extending through the chassis-less circuit boardsubstrate 602. Of course, each processor 820 may be communicativelycoupled to a different set of one or more memory devices 720 in someembodiments. Alternatively, in other embodiments, each processor 820 maybe communicatively coupled to each memory device 720. In someembodiments, the memory devices 720 may be mounted to one or more memorymezzanines on the bottom side of the chassis-less circuit boardsubstrate 602 and may interconnect with a corresponding processor 820through a ball-grid array.

Each of the processors 820 includes a heatsink 850 secured thereto. Dueto the mounting of the memory devices 720 to the bottom side 750 of thechassis-less circuit board substrate 602 (as well as the verticalspacing of the sleds 400 in the corresponding rack 240), the top side650 of the chassis-less circuit board substrate 602 includes additional“free” area or space that facilitates the use of heatsinks 850 having alarger size relative to traditional heatsinks used in typical servers.Additionally, due to the improved thermal cooling characteristics of thechassis-less circuit board substrate 602, none of the processorheatsinks 850 include cooling fans attached thereto. That is, each ofthe heatsinks 850 is embodied as a fan-less heatsinks.

Referring now to FIG. 10, in some embodiments, the sled 400 may beembodied as an accelerator sled 1000. The accelerator sled 1000 isoptimized, or otherwise configured, to perform specialized computetasks, such as machine learning, encryption, hashing, or othercomputational-intensive task. In some embodiments, for example, acompute sled 800 may offload tasks to the accelerator sled 1000 duringoperation. The accelerator sled 1000 includes various components similarto components of the sled 400 and/or compute sled 800, which have beenidentified in FIG. 10 using the same reference numbers. The descriptionof such components provided above in regard to FIGS. 6, 7, and 8 applyto the corresponding components of the accelerator sled 1000 and is notrepeated herein for clarity of the description of the accelerator sled1000.

In the illustrative accelerator sled 1000, the physical resources 620are embodied as accelerator circuits 1020. Although only two acceleratorcircuits 1020 are shown in FIG. 10, it should be appreciated that theaccelerator sled 1000 may include additional accelerator circuits 1020in other embodiments. For example, as shown in FIG. 11, the acceleratorsled 1000 may include four accelerator circuits 1020 in someembodiments. The accelerator circuits 1020 may be embodied as any typeof processor, co-processor, compute circuit, or other device capable ofperforming compute or processing operations. For example, theaccelerator circuits 1020 may be embodied as, for example, fieldprogrammable gate arrays (FPGA), application-specific integratedcircuits (ASICs), security co-processors, graphics processing units(GPUs), machine learning circuits, or other specialized processors,controllers, devices, and/or circuits.

In some embodiments, the accelerator sled 1000 may also include anaccelerator-to-accelerator interconnect 1042. Similar to theresource-to-resource interconnect 624 of the sled 600 discussed above,the accelerator-to-accelerator interconnect 1042 may be embodied as anytype of communication interconnect capable of facilitatingaccelerator-to-accelerator communications. In the illustrativeembodiment, the accelerator-to-accelerator interconnect 1042 is embodiedas a high-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the accelerator-to-accelerator interconnect1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications. In some embodiments,the accelerator circuits 1020 may be daisy-chained with a primaryaccelerator circuit 1020 connected to the NIC 832 and memory 720 throughthe I/O subsystem 622 and a secondary accelerator circuit 1020 connectedto the NIC 832 and memory 720 through a primary accelerator circuit1020.

Referring now to FIG. 11, an illustrative embodiment of the acceleratorsled 1000 is shown. As discussed above, the accelerator circuits 1020,communication circuit 830, and optical data connector 834 are mounted tothe top side 650 of the chassis-less circuit board substrate 602. Again,the individual accelerator circuits 1020 and communication circuit 830are mounted to the top side 650 of the chassis-less circuit boardsubstrate 602 such that no two heat-producing, electrical componentsshadow each other as discussed above. The memory devices 720 of theaccelerator sled 1000 are mounted to the bottom side 750 of the of thechassis-less circuit board substrate 602 as discussed above in regard tothe sled 600. Although mounted to the bottom side 750, the memorydevices 720 are communicatively coupled to the accelerator circuits 1020located on the top side 650 via the I/O subsystem 622 (e.g., throughvias). Further, each of the accelerator circuits 1020 may include aheatsink 1070 that is larger than a traditional heatsink used in aserver. As discussed above with reference to the heatsinks 870, theheatsinks 1070 may be larger than tradition heatsinks because of the“free” area provided by the memory devices 750 being located on thebottom side 750 of the chassis-less circuit board substrate 602 ratherthan on the top side 650.

Referring now to FIG. 12, in some embodiments, the sled 400 may beembodied as a storage sled 1200. The storage sled 1200 is optimized, orotherwise configured, to store data in a data storage 1250 local to thestorage sled 1200. For example, during operation, a compute sled 800 oran accelerator sled 1000 may store and retrieve data from the datastorage 1250 of the storage sled 1200. The storage sled 1200 includesvarious components similar to components of the sled 400 and/or thecompute sled 800, which have been identified in FIG. 12 using the samereference numbers. The description of such components provided above inregard to FIGS. 6, 7, and 8 apply to the corresponding components of thestorage sled 1200 and is not repeated herein for clarity of thedescription of the storage sled 1200.

In the illustrative storage sled 1200, the physical resources 620 areembodied as storage controllers 1220. Although only two storagecontrollers 1220 are shown in FIG. 12, it should be appreciated that thestorage sled 1200 may include additional storage controllers 1220 inother embodiments. The storage controllers 1220 may be embodied as anytype of processor, controller, or control circuit capable of controllingthe storage and retrieval of data into the data storage 1250 based onrequests received via the communication circuit 830. In the illustrativeembodiment, the storage controllers 1220 are embodied as relativelylow-power processors or controllers. For example, in some embodiments,the storage controllers 1220 may be configured to operate at a powerrating of about 75 watts.

In some embodiments, the storage sled 1200 may also include acontroller-to-controller interconnect 1242. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the controller-to-controller interconnect 1242 may be embodied as anytype of communication interconnect capable of facilitatingcontroller-to-controller communications. In the illustrative embodiment,the controller-to-controller interconnect 1242 is embodied as ahigh-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the controller-to-controller interconnect1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications.

Referring now to FIG. 13, an illustrative embodiment of the storage sled1200 is shown. In the illustrative embodiment, the data storage 1250 isembodied as, or otherwise includes, a storage cage 1252 configured tohouse one or more solid state drives (SSDs) 1254. To do so, the storagecage 1252 includes a number of mounting slots 1256, each of which isconfigured to receive a corresponding solid state drive 1254. Each ofthe mounting slots 1256 includes a number of drive guides 1258 thatcooperate to define an access opening 1260 of the corresponding mountingslot 1256. The storage cage 1252 is secured to the chassis-less circuitboard substrate 602 such that the access openings face away from (i.e.,toward the front of) the chassis-less circuit board substrate 602. Assuch, solid state drives 1254 are accessible while the storage sled 1200is mounted in a corresponding rack 204. For example, a solid state drive1254 may be swapped out of a rack 240 (e.g., via a robot) while thestorage sled 1200 remains mounted in the corresponding rack 240.

The storage cage 1252 illustratively includes sixteen mounting slots1256 and is capable of mounting and storing sixteen solid state drives1254. Of course, the storage cage 1252 may be configured to storeadditional or fewer solid state drives 1254 in other embodiments.Additionally, in the illustrative embodiment, the solid state driversare mounted vertically in the storage cage 1252, but may be mounted inthe storage cage 1252 in a different orientation in other embodiments.Each solid state drive 1254 may be embodied as any type of data storagedevice capable of storing long term data. To do so, the solid statedrives 1254 may include volatile and non-volatile memory devicesdiscussed above.

As shown in FIG. 13, the storage controllers 1220, the communicationcircuit 830, and the optical data connector 834 are illustrativelymounted to the top side 650 of the chassis-less circuit board substrate602. Again, as discussed above, any suitable attachment or mountingtechnology may be used to mount the electrical components of the storagesled 1200 to the chassis-less circuit board substrate 602 including, forexample, sockets (e.g., a processor socket), holders, brackets, solderedconnections, and/or other mounting or securing techniques.

As discussed above, the individual storage controllers 1220 and thecommunication circuit 830 are mounted to the top side 650 of thechassis-less circuit board substrate 602 such that no twoheat-producing, electrical components shadow each other. For example,the storage controllers 1220 and the communication circuit 830 aremounted in corresponding locations on the top side 650 of thechassis-less circuit board substrate 602 such that no two of thoseelectrical components are linearly in-line with other along thedirection of the airflow path 608.

The memory devices 720 of the storage sled 1200 are mounted to thebottom side 750 of the of the chassis-less circuit board substrate 602as discussed above in regard to the sled 400. Although mounted to thebottom side 750, the memory devices 720 are communicatively coupled tothe storage controllers 1220 located on the top side 650 via the I/Osubsystem 622. Again, because the chassis-less circuit board substrate602 is embodied as a double-sided circuit board, the memory devices 720and the storage controllers 1220 may be communicatively coupled by oneor more vias, connectors, or other mechanisms extending through thechassis-less circuit board substrate 602. Each of the storagecontrollers 1220 includes a heatsink 1270 secured thereto. As discussedabove, due to the improved thermal cooling characteristics of thechassis-less circuit board substrate 602 of the storage sled 1200, noneof the heatsinks 1270 include cooling fans attached thereto. That is,each of the heatsinks 1270 is embodied as a fan-less heatsink.

Referring now to FIG. 14, in some embodiments, the sled 400 may beembodied as a memory sled 1400. The storage sled 1400 is optimized, orotherwise configured, to provide other sleds 400 (e.g., compute sleds800, accelerator sleds 1000, etc.) with access to a pool of memory(e.g., in two or more sets 1430, 1432 of memory devices 720) local tothe memory sled 1200. For example, during operation, a compute sled 800or an accelerator sled 1000 may remotely write to and/or read from oneor more of the memory sets 1430, 1432 of the memory sled 1200 using alogical address space that maps to physical addresses in the memory sets1430, 1432. The memory sled 1400 includes various components similar tocomponents of the sled 400 and/or the compute sled 800, which have beenidentified in FIG. 14 using the same reference numbers. The descriptionof such components provided above in regard to FIGS. 6, 7, and 8 applyto the corresponding components of the memory sled 1400 and is notrepeated herein for clarity of the description of the memory sled 1400.

In the illustrative memory sled 1400, the physical resources 620 areembodied as memory controllers 1420. Although only two memorycontrollers 1420 are shown in FIG. 14, it should be appreciated that thememory sled 1400 may include additional memory controllers 1420 in otherembodiments. The memory controllers 1420 may be embodied as any type ofprocessor, controller, or control circuit capable of controlling thewriting and reading of data into the memory sets 1430, 1432 based onrequests received via the communication circuit 830. In the illustrativeembodiment, each storage controller 1220 is connected to a correspondingmemory set 1430, 1432 to write to and read from memory devices 720within the corresponding memory set 1430, 1432 and enforce anypermissions (e.g., read, write, etc.) associated with sled 400 that hassent a request to the memory sled 1400 to perform a memory accessoperation (e.g., read or write).

In some embodiments, the memory sled 1400 may also include acontroller-to-controller interconnect 1442. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the controller-to-controller interconnect 1442 may be embodied as anytype of communication interconnect capable of facilitatingcontroller-to-controller communications. In the illustrative embodiment,the controller-to-controller interconnect 1442 is embodied as ahigh-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the controller-to-controller interconnect1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications. As such, in someembodiments, a memory controller 1420 may access, through thecontroller-to-controller interconnect 1442, memory that is within thememory set 1432 associated with another memory controller 1420. In someembodiments, a scalable memory controller is made of multiple smallermemory controllers, referred to herein as “chiplets”, on a memory sled(e.g., the memory sled 1400). The chiplets may be interconnected (e.g.,using EMIB (Embedded Multi-Die Interconnect Bridge)). The combinedchiplet memory controller may scale up to a relatively large number ofmemory controllers and I/O ports, (e.g., up to 16 memory channels). Insome embodiments, the memory controllers 1420 may implement a memoryinterleave (e.g., one memory address is mapped to the memory set 1430,the next memory address is mapped to the memory set 1432, and the thirdaddress is mapped to the memory set 1430, etc.). The interleaving may bemanaged within the memory controllers 1420, or from CPU sockets (e.g.,of the compute sled 800) across network links to the memory sets 1430,1432, and may improve the latency associated with performing memoryaccess operations as compared to accessing contiguous memory addressesfrom the same memory device.

Further, in some embodiments, the memory sled 1400 may be connected toone or more other sleds 400 (e.g., in the same rack 240 or an adjacentrack 240) through a waveguide, using the waveguide connector 1480. Inthe illustrative embodiment, the waveguides are 64 millimeter waveguidesthat provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit)lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32Ghz. In other embodiments, the frequencies may be different. Using awaveguide may provide high throughput access to the memory pool (e.g.,the memory sets 1430, 1432) to another sled (e.g., a sled 400 in thesame rack 240 or an adjacent rack 240 as the memory sled 1400) withoutadding to the load on the optical data connector 834.

Referring now to FIG. 15, a system for executing one or more workloads(e.g., applications) may be implemented in accordance with the datacenter 100. In the illustrative embodiment, the system 1510 includes anorchestrator server 1520, which may be embodied as a managed nodecomprising a compute device (e.g., a compute sled 800) executingmanagement software (e.g., a cloud operating environment, such asOpenStack) that is communicatively coupled to multiple sleds 400including a large number of compute sleds 1530 (e.g., each similar tothe compute sled 800), memory sleds 1540 (e.g., each similar to thememory sled 1400), accelerator sleds 1550 (e.g., each similar to thememory sled 1000), and storage sleds 1560 (e.g., each similar to thestorage sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 maybe grouped into a managed node 1570, such as by the orchestrator server1520, to collectively perform a workload (e.g., an application 1532executed in a virtual machine or in a container). The managed node 1570may be embodied as an assembly of physical resources 620, such asprocessors 820, memory resources 720, accelerator circuits 1020, or datastorage 1250, from the same or different sleds 400. Further, the managednode may be established, defined, or “spun up” by the orchestratorserver 1520 at the time a workload is to be assigned to the managed nodeor at any other time, and may exist regardless of whether any workloadsare presently assigned to the managed node. In the illustrativeembodiment, the orchestrator server 1520 may selectively allocate and/ordeallocate physical resources 620 from the sleds 400 and/or add orremove one or more sleds 400 from the managed node 1570 as a function ofquality of service (QoS) targets (e.g., performance targets associatedwith a throughput, latency, instructions per second, etc.) associatedwith a service level agreement for the workload (e.g., the application1532). In doing so, the orchestrator server 1520 may receive telemetrydata indicative of performance conditions (e.g., throughput, latency,instructions per second, etc.) in each sled 400 of the managed node 1570and compare the telemetry data to the quality of service targets todetermine whether the quality of service targets are being satisfied. Ifthe so, the orchestrator server 1520 may additionally determine whetherone or more physical resources may be deallocated from the managed node1570 while still satisfying the QoS targets, thereby freeing up thosephysical resources for use in another managed node (e.g., to execute adifferent workload). Alternatively, if the QoS targets are not presentlysatisfied, the orchestrator server 1520 may determine to dynamicallyallocate additional physical resources to assist in the execution of theworkload (e.g., the application 1532) while the workload is executing

Additionally, in some embodiments, the orchestrator server 1520 mayidentify trends in the resource utilization of the workload (e.g., theapplication 1532), such as by identifying phases of execution (e.g.,time periods in which different operations, each having differentresource utilizations characteristics, are performed) of the workload(e.g., the application 1532) and pre-emptively identifying availableresources in the data center 100 and allocating them to the managed node1570 (e.g., within a predefined time period of the associated phasebeginning). In some embodiments, the orchestrator server 1520 may modelperformance based on various latencies and a distribution scheme toplace workloads among compute sleds and other resources (e.g.,accelerator sleds, memory sleds, storage sleds) in the data center 100.For example, the orchestrator server 1520 may utilize a model thataccounts for the performance of resources on the sleds 400 (e.g., FPGAperformance, memory access latency, etc.) and the performance (e.g.,congestion, latency, bandwidth) of the path through the network to theresource (e.g., FPGA). As such, the orchestrator server 1520 maydetermine which resource(s) should be used with which workloads based onthe total latency associated with each potential resource available inthe data center 100 (e.g., the latency associated with the performanceof the resource itself in addition to the latency associated with thepath through the network between the compute sled executing the workloadand the sled 400 on which the resource is located).

In some embodiments, the orchestrator server 1520 may generate a map ofheat generation in the data center 100 using telemetry data (e.g.,temperatures, fan speeds, etc.) reported from the sleds 400 and allocateresources to managed nodes as a function of the map of heat generationand predicted heat generation associated with different workloads, tomaintain a target temperature and heat distribution in the data center100. Additionally or alternatively, in some embodiments, theorchestrator server 1520 may organize received telemetry data into ahierarchical model that is indicative of a relationship between themanaged nodes (e.g., a spatial relationship such as the physicallocations of the resources of the managed nodes within the data center100 and/or a functional relationship, such as groupings of the managednodes by the customers the managed nodes provide services for, the typesof functions typically performed by the managed nodes, managed nodesthat typically share or exchange workloads among each other, etc.).Based on differences in the physical locations and resources in themanaged nodes, a given workload may exhibit different resourceutilizations (e.g., cause a different internal temperature, use adifferent percentage of processor or memory capacity) across theresources of different managed nodes. The orchestrator server 1520 maydetermine the differences based on the telemetry data stored in thehierarchical model and factor the differences into a prediction offuture resource utilization of a workload if the workload is reassignedfrom one managed node to another managed node, to accurately balanceresource utilization in the data center 100.

To reduce the computational load on the orchestrator server 1520 and thedata transfer load on the network, in some embodiments, the orchestratorserver 1520 may send self-test information to the sleds 400 to enableeach sled 400 to locally (e.g., on the sled 400) determine whethertelemetry data generated by the sled 400 satisfies one or moreconditions (e.g., an available capacity that satisfies a predefinedthreshold, a temperature that satisfies a predefined threshold, etc.).Each sled 400 may then report back a simplified result (e.g., yes or no)to the orchestrator server 1520, which the orchestrator server 1520 mayutilize in determining the allocation of resources to managed nodes.

Referring now to FIG. 16, a system 1610 for providing in-processorworkload phase detection may be implemented in accordance with the datacenter 100 described above with reference to FIG. 1. In the illustrativeembodiment, the system 1610 includes an orchestrator server 1620communicatively coupled to multiple sleds including a compute sled 1630,a memory sled 1640, a storage sled 1650, and an accelerator sled 1660.One or more of the sleds 1630, 1640, 1650 and 1660 may be grouped into amanaged node, such as by the orchestrator server 1620, to collectivelyperform a workload, such as an application. A managed node may beembodied as an assembly of resources, such as compute resources, memoryresources, storage resources, or other resources, from the same ordifferent sleds or racks. Further, a managed node may be established,defined, or “spun up” by the orchestrator server 1620 at the time aworkload is to be assigned to the managed node or at any other time, andmay exist regardless of whether any workloads are presently assigned tothe managed node. The system 1610 may be located in a data center andprovide storage and compute services (e.g., cloud services) to a clientdevice 1614 that is in communication with the system 1610 through anetwork 1612. The orchestrator server 1620 may support a cloud operatingenvironment, such as OpenStack, and managed nodes established by theorchestrator server 1620 may execute one or more applications orprocesses (i.e., workloads), such as in virtual machines or containers,on behalf of a user of the client device 1614.

In the illustrative embodiment, the compute sled 1630 includes a centralprocessing unit (CPU) 1632 (e.g., a processor or other device orcircuitry capable of performing a series of operations) that executes aworkload (e.g., the application 1634). The memory sled 1640 includes oneor more memory devices 1642 (e.g., non-volatile memory, such asbyte-addressable, write in-place non-volatile memory, or volatilememory, such as dynamic random-access memory (DRAM)). The storage sled1650 includes one or more storage devices 1652, (e.g., hard disk drives(HDDs), solid state drives (SSDs), etc.). The accelerator sled 1660, inthe illustrative embodiment, includes one or more accelerator devices1662. As such, each accelerator device 1662 may be embodied as anydevice or circuitry (e.g., a specialized processor, an FPGA, an ASIC, agraphics processing unit (GPU), reconfigurable hardware, etc.) capableof accelerating the execution of a function.

Referring now to FIG. 17, the compute sled 1630 may be embodied as anytype of compute device capable of performing the functions describedherein, including receiving telemetry data from a performance monitorunit executing in the compute sled 1630, determining, from a phaselookup table in the compute sled 1630, a resource utilization phase of aworkload based on the telemetry data, updating a workload fingerprintbased on the resource utilization phase, and outputting the workloadfingerprint to an area of memory in the compute sled 1630 reserved bythe performance monitor unit.

As shown in FIG. 17, the illustrative compute sled 1630 includes acompute engine 1702, an input/output (I/O) subsystem 1712, communicationcircuitry 1714, and one or more data storage devices 1718. Of course, inother embodiments, the compute sled 1630 may include other or additionalcomponents, such as those commonly found in a computer (e.g., display,peripheral devices, etc.). Additionally, in some embodiments, one ormore of the illustrative components may be incorporated in, or otherwiseform a portion of, another component.

The compute engine 1702 may be embodied as any type of device orcollection of devices capable of performing various compute functionsdescribed below. In some embodiments, the compute engine 1702 may beembodied as a single device such as an integrated circuit, an embeddedsystem, a field-programmable gate array (FPGA), a system-on-a-chip(SoC), or other integrated system or device. Additionally, in someembodiments, the compute engine 1702 includes or is embodied as aprocessor 1704 (e.g., the CPU 1632) and a memory 1710. The processor1704 may be embodied as any type of processor capable of performing thefunctions described herein. For example, the processor 1704 may beembodied as a single or multi-core processor(s), a microcontroller, orother processor or processing/controlling circuit. In some embodiments,the processor 1704 may be embodied as, include, or be coupled to anFPGA, an application specific integrated circuit (ASIC), reconfigurablehardware or hardware circuitry, or other specialized hardware tofacilitate performance of the functions described herein. Additionally,in the illustrative embodiment, the processor 1704 includes a phasedetection logic unit 1605, which may be embodied as any circuitry ordevice (e.g., a microcontroller, co-processor, etc.).

As further described herein, the phase detection logic unit 1705 mayprogram components in the processor 1704 to monitor resource utilizationduring execution of a workload and compare the monitored utilizationagainst a phase lookup table to determine a present workload phase. Theprocessor 1704 also includes one or more model-specific registers (MSRs)1706. The MSRs 1706 may be embodied as instruction set architecture(ISA) registers (e.g., x86 instruction set registers) that control oneor more operations of the processor 1704. Illustratively, the MSRs 1706include a control MSR 1707 that stores values that the processor 1704may interpret to perform some operation as a function of the value, suchas starting or pausing counters, reserving areas of memory, and thelike. The processor 1704 also includes one or more general purposeregisters (GPRs) to store data and addresses during operation of theprocessor 1704. Further, the processor 1704 includes a performancemonitor unit (PMU) 1709, which, in operation, monitors various telemetrydata indicative of the performance and conditions in the compute sled(e.g., the number of cache hits/misses, cycles per instruction, cacheoccupancy, core frequency, etc.) using counters during the execution ofa workload. The PMU 1709 may be embodied as any circuitry or device thatreceives performance event signals from the processor 1704.

The memory 1710 may be embodied as any type of volatile or non-volatilememory or data storage capable of performing the functions describedherein. Volatile memory may be a storage medium that requires power tomaintain the state of data stored by the medium. Non-limiting examplesof volatile memory may include various types of random access memory(RAM), such as dynamic random access memory (DRAM) or static randomaccess memory (SRAM). One particular type of DRAM that may be used in amemory module is synchronous dynamic random access memory (SDRAM). Inparticular embodiments, DRAM of a memory component may comply with astandard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2Ffor DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM,JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 forLPDDR3, and JESD209-4 for LPDDR4 (these standards are available atwww.jedec.org). Such standards (and similar standards) may be referredto as DDR-based standards and communication interfaces of the storagedevices that implement such standards may be referred to as DDR-basedinterfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include future generation nonvolatile devices, such as a threedimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), orother byte addressable write-in-place nonvolatile memory devices. In oneembodiment, the memory device may be or may include memory devices thatuse chalcogenide glass, multi-threshold level NAND flash memory, NORflash memory, single or multi-level Phase Change Memory (PCM), aresistive memory, nanowire memory, ferroelectric transistor randomaccess memory (FeTRAM), anti-ferroelectric memory, magnetoresistiverandom access memory (MRAM) memory that incorporates memristortechnology, resistive memory including the metal oxide base, the oxygenvacancy base and the conductive bridge Random Access Memory (CB-RAM), orspin transfer torque (STT)-MRAM, a spintronic magnetic junction memorybased device, a magnetic tunneling junction (MTJ) based device, a DW(Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristorbased memory device, or a combination of any of the above, or othermemory. The memory device may refer to the die itself and/or to apackaged memory product.

In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™memory) may comprise a transistor-less stackable cross pointarchitecture in which memory cells sit at the intersection of word linesand bit lines and are individually addressable and in which bit storageis based on a change in bulk resistance. In some embodiments, all or aportion of the memory 1710 may be integrated into the processor 1704. Inoperation, the memory 1710 may store various software and data usedduring operation, such as a phase lookup table indicative of an area ofthe memory 1710 that is reserved for storing resource utilizationphases. As further described herein, the phase detection logic unit 1705may evaluate the present resource utilization of the compute sled 1630relative to the phase lookup table to determine a present phase of aworkload execution.

The compute engine 1702 is communicatively coupled to other componentsof the compute sled 1630 via the I/O subsystem 1712, which may beembodied as circuitry and/or components to facilitate input/outputoperations with the compute engine 1702 (e.g., with the processor 1704and/or the memory 1710) and other components of the compute sled 1702.For example, the I/O subsystem 1712 may be embodied as, or otherwiseinclude, memory controller hubs, input/output control hubs, integratedsensor hubs, firmware devices, communication links (e.g., point-to-pointlinks, bus links, wires, cables, light guides, printed circuit boardtraces, etc.), and/or other components and subsystems to facilitate theinput/output operations. In some embodiments, the I/O subsystem 1712 mayform a portion of a SoC and be incorporated, along with one or more ofthe processor 1704, the memory 1710, and other components of the computesled 1630, into the compute engine 1702.

The communication circuitry 1714 may be embodied as any communicationcircuit, device, or collection thereof, capable of enablingcommunications over the network 1612 between the compute sled 1630 andanother compute device (e.g., the memory sled 1640, storage sled 1650,the accelerator sled 1660, etc.). The communication circuitry 1714 maybe configured to use any one or more communication technology (e.g.,wired or wireless communications) and associated protocols (e.g.,Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.

The illustrative communication circuitry 1714 includes a networkinterface controller (NIC) 1716, which may also be referred to as a hostfabric interface (HFI). The NIC 1716 may be embodied as one or moreadd-in-boards, daughter cards, network interface cards, controllerchips, chipsets, or other devices that may be used by the compute sled1630 to connect with another compute device (e.g., the memory sled 1640,the storage sled 1650, the accelerator sled 1660, etc.). In someembodiments, the NIC 1716 may be embodied as part of an SoC thatincludes one or more processors, or included on a multichip package thatalso contains one or more processors. In some embodiments, the NIC 1716may include a local processor (not shown) and/or a local memory (notshown) that are both local to the NIC 1716. In such embodiments, thelocal processor of the NIC 1716 may be capable of performing one or moreof the functions of the compute engine 1702 described herein.Additionally or alternatively, in such embodiments, the local memory ofthe NIC 1716 may be integrated into one or more components of thecompute sled 1630 at the board level, socket level, chip level, and/orother levels.

The one or more illustrative data storage devices 1718, may be embodiedas any type of devices configured for short-term or long-term storage ofdata such as, for example, memory devices and circuits, memory cards,hard disk drives, solid-state drives, or other data storage devices.Each data storage device 1718 may include a system partition that storesdata and firmware code for the data storage device 1718. Each datastorage device 1718 may also include an operating system partition thatstores data files and executables for an operating system. Additionallyor alternatively, the compute sled 1630 may include one or moreperipheral devices 1720. Such peripheral devices 1720 may include anytype of peripheral device commonly found in a compute device such as adisplay, speakers, a mouse, a keyboard, and/or other input/outputdevices, interface devices, and/or other peripheral devices.

Referring now to FIG. 18, the compute sled 1630 may establish anenvironment 1800 during operation. The illustrative environment 1800includes a network communicator 1820, a phase detector 1830, and aremediation engine 1840. Each of the components of the environment 1800may be embodied as hardware, firmware, software, or a combinationthereof. As such, in some embodiments, one or more of the components ofthe environment 1800 may be embodied as circuitry or a collection ofelectrical devices (e.g., network communicator circuitry 1820, phasedetector circuitry 1830, remediation engine circuitry 1840, etc.). Itshould be appreciated that, in such embodiments, one or more of thenetwork communicator circuitry 1820, phase detector circuitry 1830, orremediation engine circuitry 1840 may form a portion of one or more ofthe compute engine 1702, the phase detection logic unit 1705, thecommunication circuitry 1714, the I/O subsystem 1712, and/or othercomponents of the compute sled 1630.

In the illustrative embodiment, the environment 1800 includes telemetrydata 1802, which may be embodied as any data indicative of theperformance (e.g., cache occupancy, cache hits/misses, core frequency,instructions retired, bytes read from/written to memory controllers, andthe like) and other conditions, such as power usage, of the compute sled1630. Additionally, in the illustrative embodiment, the environment 1800includes a phase lookup table 1804 which may be embodied as any dataindicative of one or more phases of a workload, determined as a functionof the telemetry data 1802. More specifically, the phase lookup table1804 is a structure that may be populated with phase data (e.g., phasedata 1806, described herein) at boot time by the BIOS or after boot,such as by the operating system of the compute sled 1630. The phaselookup table 1804 may be indexed based on various characteristics of aworkload phase (e.g., by a time interval, by a threshold of a givenmetric, etc.). The compute sled 1630 may evaluate the phase lookup table1804 to determine a present phase during execution of a workload.Additionally, in the illustrative embodiment, the environment 1800includes phase data 1806, which may be embodied as any data indicativeof a resource utilization phase (e.g., period of utilization of aparticular type of resource above a threshold amount) and lengths oftime of those phases (e.g., phase residencies) for a given workload.Patterns of the phase data 1806 may indicate a “fingerprint” of resourceutilization for the workload. In particular, the workload fingerprintincludes a phase residency matrix indicative of an amount of time that aworkload will likely reside in a present phase. The workload fingerprintalso includes a phase transition matrix indicative of an amount of timeremaining before the workload will transition to a subsequent phase,and, in the illustrative embodiment, indicators of the likelihood ofdifferent possible subsequent phases following the present phase (e.g.,a 60% chance that phase B will follow phase A and a 40% chance thatphase C will follow phase A). In the illustrative embodiment, the policydata 1808 may be any data indicative of predefined preferences anddirectives for managing resource utilization in the compute sled 1630.The compute sled 1630 may adjust resources therein based on a workloadfingerprint and the policy data 1808.

In the illustrative environment 1800, the network communicator 1820,which may be embodied as hardware, firmware, software, virtualizedhardware, emulated architecture, and/or a combination thereof asdiscussed above, is configured to facilitate inbound and outboundnetwork communications (e.g., network traffic, network packets, networkflows, etc.) to and from the compute sled 1630, respectively. To do so,the network communicator 1820 is configured to receive and process datapackets from one system or computing device (e.g., the orchestratorserver 1620, memory sled 1640, storage sled 1650, accelerator sled 1660,etc.) and to prepare and send data packets to another computing deviceor system. Accordingly, in some embodiments, at least a portion of thefunctionality of the network communicator 1820 may be performed by thecommunication circuitry 1714, and, in the illustrative embodiment, bythe NIC 1716.

The phase detector 1830, which may be embodied as hardware, firmware,software, virtualized hardware, emulated architecture, and/or acombination thereof, is configured to program the processor 1704 tomonitor performance events in the compute sled 1630 during execution ofone or more workloads, detect workload phases based on the monitoredperformance events, update a workload fingerprint, and publish theworkload fingerprint. To do so, in the illustrative embodiment, thephase detector 1830 includes a monitor component 1832, a detectioncomponent 1834, a fingerprinter component 1836, and a publishercomponent 1838.

In an embodiment, the monitor component 1832 is configured to performinitialization of phase detection functions in the processor. To do so,the monitor component 1832 may write leaf values (e.g., via a WRMSRinstruction) to the control MSR 1707. For example, the monitor component1832 may be configured to reserve areas of memory used by the phasedetector 1830 to store the phase lookup table 1804 and workloadfingerprint data by writing a leaf value indicative of an instruction toreserve the areas of memory. In addition, the monitor component 1832 mayprogram components in the compute engine 1702, such as the PMU 1709, tomonitor performance events occurring in the compute sled 1630 such as byconfiguring the PMU 1709 to output counter values for a given event(e.g., cache events relating to cache hits/misses per thousandinstructions or cache occupancy, instruction execution events affectingcycles per instruction, etc.) to an MSR 1706 or GPR 1708. Further, themonitor component 1832 may initiate counters in the PMU 1709 by issuinga WRMSR instruction to do so. Once initiated, the PMU 1709, in theillustrative embodiment, executes the counters to monitor the programmedevents.

In the illustrative embodiment, the detection component 1834 isconfigured to retrieve counter values output to the registers by the PMU1709. In particular, the detection component 1834 may pause counters ofthe PMU 1709 (e.g., by writing a leaf value indicative of an instructionto pause the counters) at a predefined interval and obtain the countervalues representative of the telemetry data 1802 from the MSRs 1706 andGPRs 1708. The fingerprinter component 1836, in the illustrativeembodiment, is configured to determine a present phase based on theretrieved telemetry data 1802. In particular, the fingerprintercomponent 1836 evaluates the telemetry data 1802 relative to the phaselookup table 1804 and identifies a matching tuple (or a relatively closematch) to a given entry in the phase lookup table 1804. The matchedentry may be indicative of the present phase of the workload execution.Further, the fingerprinter component 1836 may update a workloadfingerprint as a function of the determined present phase. The publishercomponent 1838, in the illustrative embodiment, is configured to exportthe workload fingerprint to the area of memory reserved by the monitorcomponent 1832. The reserved area of memory is accessible by variousconsumers, such as the remediation engine 1840, user space analyticsapplications, the orchestrator server 1620, and the like.

Various components of the phase detector 1830 may write leaf values toand/or read leaf values from the control MSR 1707. Table 1, depictedbelow, summarizes each leaf value and its corresponding interpretation,in the illustrative embodiment.

TABLE 1 Leaf Value Description 1 Program PMU registers with eventsProgram address 1 (e.g., start location of the phase lookup table)Program address 2 (e.g., location where output is stored, where the sizeof the area depends on a total number of hardware threads present in thesystem). 2 Start counter Enable periodic event to log phase data 4 Stopcounter Export telemetry data to memory

In the illustrative embodiment, the remediation engine 1840 isconfigured to evaluate the present workload fingerprint relative to thepolicy data 1808 and determine whether any remedial actions should beperformed within the compute sled 1630. Remedial actions may includereallocating compute resources to a particular workload, assigning agiven workload to the compute sled 1630, and the like. For example, thepolicy data 1808 may indicate that if the cache miss rate is above acertain threshold, then the remediation engine 1840 should reduce thecache size (e.g., by an amount determined as a function of the cachemiss rate). As another example, the policy data 1808 may indicate thatif the processor capacity exceeds a specified threshold, then theremediation engine 1840 should allocate the excess processor capacitytowards a given workload.

Referring now to FIG. 19, the compute sled 1630, in operation, mayexecute a method 1900 to provide in-processor workload phase detection.As shown, the method 1900 begins at boot of the platform. In block 1902,the BIOS of the compute sled 1630 reserves an area of memory for thephase lookup table. Further, the BIOS reserves an area of memory tostore a workload fingerprint output by the processor 1704 in operation.In block 1904, the compute sled 1630 programs the PMU 1709 to monitortelemetry data. In particular, in block 1906, the compute sled 1630writes, to the control MSR, a leaf value indicative of programming thePMU. In block 1908, the BIOS passes the reserved memory addresses to theprocessor 1704. The processor 1704 may write the addresses to one of theMSRs 1706. In block 1910, the processor 1704 programs the PMU 1709 oneach hardware thread with a predefined set of events to monitor.

In block 1912, the compute sled 1630 initializes the phase lookup table.In particular, in block 1914, the compute sled 1630 executes one or moreworkloads using a training data set as input, which may be indicative ofany metrics data used for a variety of workloads executing in the system1610. In block 1916, the compute sled 1630 collects telemetry dataduring the execution of the one or more workloads. In block 1918, thecompute sled 1630 generates a resource utilization phase model based onthe collected telemetry data. The resource utilization phase modelallows the compute sled 1630 to detect a given phase corresponding to agiven tuple of training data. For each metric in the telemetry data, thecompute sled 1630 identifies the highest possible value or applicablethreshold. The compute sled 1630 may use the threshold to discretize thetelemetry data metrics into higher granularity values. Discretizing themetrics transforms continuous data into a discrete data point. In block1920, the compute sled 1630 populates the phase lookup table with thediscretized telemetry data.

In block 1922, the compute sled 1630 activates monitoring of telemetrydata via the PMU 1709. In doing so, in the illustrative embodiment, thecompute sled 1630 writes a leaf value to the control MSR 1707, asindicated in block 1924. The written leaf value is indicative of aninstruction for activating event counters in the PMU 1709. In block1926, the PMU 1709 starts the counters to begin monitoring the telemetrydata. The processor 1704 may evaluate the control MSR 1707 (e.g., byperforming a RDMSR operation on the control MSR 1707) to obtain thewritten leaf value and cause the PMU 1709 to start, in response to thewritten leaf value, the counters.

Referring now to FIG. 20, the PMU 1709 of the processor 1704 may monitorpredefined performance events. In the illustrative embodiment, and as inblock 1928, the compute sled 1630 executes a workload for the system1610 (e.g., a workload assigned by the orchestrator server 1620). Eventcounters in the PMU 1709 may be associated with various resources tomonitor, such as cache occupancy, core frequency, cache hit/miss rateper thousand instructions, elapsed core clock ticks, instructionsretired, memory controller read/written bytes, data traffic transferredby interconnect links, etc. The compute sled 1630, in the illustrativeembodiment, selectively pauses the event counters to retrieve countervalues for a given point in time of execution of the workload. In block1930, the compute sled 1630 determines whether to pause event monitoringin the PMU 1709. For example, the compute sled 1630 may do so at aspecified interval or upon receipt of a request to the processor 1704 todo so. If not, then the event counters in the PMU 1709 remain active.

Otherwise, in block 1932, the compute sled 1630 pauses event monitoringby the PMU 1709. For example, to do so, the compute sled 1630 may writea leaf value to the control MSR 1707 indicative of an instruction topause the event counters, as indicated in block 1934. The processor 1704reads the control MSR 1707 and causes the PMU 1709 to pause the eventcounters. In block 1936, the compute sled 1630 retrieves telemetry datafrom the PMU 1709. In particular, the processor 1704 may retrieve thecounter values from the MSRs 1706 and/or GPRs 1708 that store thecounter values corresponding to each monitored event.

In block 1938, the compute sled 1630 determines a present phase as afunction of the retrieved telemetry data. In particular, the computesled 1630 may discretize the telemetry data, as indicated in block 1940.For example, the compute sled 1630 may discretize the data in the mannerdescribed above. Further, Table 2 below depicts an examplediscretization of a telemetry data metric for IPC:

TABLE 2 Mispredicts per thousand Occupancy - divide current IPC - Dividecurrent IPC by 2 instructions (MPKI) occupancy by LLC size RangeIdentifier Range Identifier Range Identifier  0-0.5 L 0-5  L 0.00-0.33 L0.5-1.0 M 5-20 M 0.33-0.66 M >1 H >20 H 0.66-1.00 H

In Table 2, the IPC range of 0-0.5 is marked ‘L’ (low), the IPC range of0.15-1.0 is marked ‘M’ (medium), and values higher than 1.0 are markedas ‘H’ (high). The MPKI and cache occupancy values are similarlydiscretized. In block 1942, the compute sled 1630 queries the phaselookup table 1804 using the discretized telemetry data as input. Table 3provides an example of a phase lookup table:

TABLE 3 Cache Occupancy IPC LLC Miss Phase Number L H L 0 L L H 1 M H L2 L M L 3

Table 3 tracks metrics corresponding to cache occupancy, instructionsper cycle (IPC), and low-level cache (LLC) misses per thousandinstructions. The compute sled 1630 may input the discretized telemetrydata as a tuple of metric values, such as (cache occupancy value, IPCvalue, LLC miss value). In block 1944, the compute sled 1630 retrievesthe present phase from the phase lookup table based on the query. UsingTable 3 as an example, if the monitored telemetry data, afterdiscretization, corresponds to a low cache occupancy, low IPC, and highLLC miss rate, then the present phase corresponds to phase 1.

In block 1946, the compute sled 1630 updates a workload fingerprintbased on the present phase retrieved from the phase lookup table 1804.In doing so, the compute sled 1630, in the illustrative embodiment,recalculates the phase residency and transition matrices based on thepresent phase, as indicated in block 1948. For example, the compute sled1630 may extend the phase residency for the present phase if the phasehas lasted longer than the time period indicated in the phase residencymatrix. Conversely, the compute sled 1630 may shorten the phaseresidency for the previous phase if the workload transitioned to asubsequent phase earlier than indicated in the phase residency matrix.The compute sled 1630 may also update the probability of the subsequentphase being a particular phase (e.g., phase B) in response todetermining that the particular phase (e.g., phase B) occurred after theprevious phase. Additionally, the compute sled 1630 outputs the workloadfingerprint, as indicated in block 1950. In particular, the compute sled1630 may write the workload fingerprint to the reserved output locationin the memory 1710, as indicated in block 1952. To do so, the computesled 1630 may determine the memory address reserved by the BIOS as theoutput location for the workload fingerprint. The compute sled 1630 maythen access the memory address and write the workload fingerprintindicative of the present phase at the memory address.

By writing the workload fingerprint to the reserved area of memory,consumers such as user space applications and the orchestrator server1620 may retrieve the workload fingerprint and analyze the workloadfingerprint to perform, in response, some further action. Additionallyor alternatively, the remediation engine 1840 may analyze the workloadfingerprint and potentially perform, in response to the analysis, aremedial action. Performing the analysis locally (e.g., on the computesled 1630) offloads this function from the orchestrator server 1620,enabling the orchestrator server 1620 to more efficiently perform otherdata center wide management operations. Referring now to FIG. 21, inblock 1954, the compute sled 1630 (via the remediation engine 1840)retrieves the workload fingerprint from the reserved area of memory.

In block 1956, the compute sled 1630 evaluates the workload fingerprintrelative to policy data. The workload fingerprint may satisfy one ormore conditions specified in the policy data that cause some remedialaction to be performed. In block 1958, the compute sled 1630 determinesa remedial action to perform as a function of the policy data. Thepolicy data may specify the remedial action to perform. For example, thepolicy data may indicate that if cache occupancy is presently low, thenthe cache size should be reduced. In block 1960, the compute sled 1630performs the remedial action, if any. Continuing the example, thecompute sled 1630 may reduce the cache size for a given workload.Subsequently, the method 1900 loops back to block 1922 of FIG. 19, inwhich the compute sled 1630 continues monitoring the telemetry data withthe PMU 1709.

EXAMPLES

Illustrative examples of the technologies disclosed herein are providedbelow. An embodiment of the technologies may include any one or more,and any combination of, the examples described below.

Example 1 includes a sled, comprising communication circuitry and acompute engine comprising a performance monitor unit, wherein thecompute engine is to (i) obtain telemetry data from the performancemonitor unit, wherein the performance monitor unit is to producetelemetry data indicative of resource utilization and workloadperformance by the sled as one or more workloads are executed, (ii)determine, from a lookup table indicative of a plurality of resourceutilization phases, a resource utilization phase based on the obtainedtelemetry data, (iii) update a workload fingerprint based on thedetermined resource utilization phase, and (iv) output the workloadfingerprint.

Example 2 includes the subject matter of Example 1, and wherein tooutput the workload fingerprint comprises to output the workloadfingerprint to an area of memory in the sled reserved by the performancemonitor unit.

Example 3 includes the subject matter of any of Examples 1 and 2, andwherein the compute engine is further to retrieve the workloadfingerprint from the area of memory; evaluate the workload fingerprintrelative to policy data; determine a remedial action to perform inresponse to the evaluation; and perform the remedial action.

Example 4 includes the subject matter of any of Examples 1-3, andwherein the compute engine is further to initialize the lookup tablewith the plurality of resource utilization phases.

Example 5 includes the subject matter of any of Examples 1-4, andwherein to initialize the lookup table with the plurality of resourceutilization phases comprises to execute the one or more workloads withtraining data as input; generate a resource utilization phase modelbased on telemetry data collected from the execution of the one or moreworkloads with the training data as input; and populate the lookup tablewith discretized telemetry data determined based on the resourceutilization phase model.

Example 6 includes the subject matter of any of Examples 1-5, andwherein the compute engine is further to program the performance monitorunit to monitor the telemetry data at boot time of the sled.

Example 7 includes the subject matter of any of Examples 1-6, andwherein to program the performance monitor unit comprises to write avalue to a register indicative of an instruction to configure, in theperformance monitor unit, one or more events to monitor during theexecution of the one or more workloads.

Example 8 includes the subject matter of any of Examples 1-7, andwherein to determine the resource utilization phase based on theobtained telemetry data comprises to discretize the telemetry data;query the lookup table using the discretized telemetry data; andreceive, in response to the query, the resource utilization phase fromthe lookup table.

Example 9 includes the subject matter of any of Examples 1-8, andwherein the resource utilization phase is a first resource utilizationphase and the workload fingerprint comprises a residency matrixindicative of a time duration that a workload remains in a givenresource utilization phase and further comprises a transitionprobability matrix indicative of a likelihood that the workloadtransitions to a second resource utilization phase.

Example 10 includes the subject matter of any of Examples 1-9, andwherein to update the workload fingerprint comprises to recalculate theresidency matrix and the transition probability matrix based on thedetermined resource utilization phase.

Example 11 includes the subject matter of any of Examples 1-10, andwherein to obtain the telemetry data comprises to write a value to aregister indicative of an instruction to start a counter in theperformance monitor unit; and cause, in response to the write of thevalue to the register, the performance monitor unit to start thecounter.

Example 12 includes the subject matter of any of Examples 1-11, andwherein the compute engine is further to write a second value to theregister indicative of an instruction to pause the counter in theperformance monitor unit.

Example 13 includes the subject matter of any of Examples 1-12, andwherein to obtain the telemetry data comprises to retrieve one or moreof a number of cache misses per thousand instructions, a number ofcycles per instruction, or cache occupancy data.

Example 14 includes a method, comprising obtaining, by a sled thatincludes a performance monitor unit, telemetry data produced by theperformance monitor unit, wherein the telemetry data is indicative ofresource utilization and workload performance by the sled as one or moreworkloads are executed; determining, by the sled and from a lookup tableindicative of a plurality of resource utilization phases, a resourceutilization phase based on the obtained telemetry data; updating, by thesled, a workload fingerprint based on the determined resourceutilization phase; and outputting, by the sled, the workloadfingerprint.

Example 15 includes the subject matter of Example 14, and whereinoutputting the workload fingerprint comprises outputting the workloadfingerprint to an area of memory in the sled reserved by the performancemonitor unit.

Example 16 includes the subject matter of any of Examples 14 and 15, andfurther including retrieving, by the sled, the workload fingerprint fromthe area of memory; evaluating, by the sled, the workload fingerprintrelative to policy data; determining, by the sled, a remedial action toperform in response to the evaluation; and performing, by the sled, theremedial action.

Example 17 includes the subject matter of any of Examples 14-16, andfurther including initializing, by the sled, the lookup table with theplurality of resource utilization phases.

Example 18 includes the subject matter of any of Examples 14-17, andwherein initializing the lookup table with the plurality of resourceutilization phases comprises executing, by the sled, the one or moreworkloads with training data as input; generating, by the sled, aresource utilization phase model based on telemetry data collected fromthe execution of the one or more workloads with the training data asinput; and populating, by the sled, the lookup table with discretizedtelemetry data determined based on the resource utilization phase model.

Example 19 includes the subject matter of any of Examples 14-18, andfurther including programming, by the sled, the performance monitor unitto monitor the telemetry data at boot time of the sled.

Example 20 includes the subject matter of any of Examples 14-19, andwherein programming the performance monitor unit comprises writing avalue to a register indicative of an instruction to configure, in theperformance monitor unit, one or more events to monitor during theexecution of the one or more workloads.

Example 21 includes the subject matter of any of Examples 14-20, andwherein determining the resource utilization phase based on the obtainedtelemetry data comprises discretizing the telemetry data; querying thelookup table using the discretized telemetry data; and receiving, inresponse to the query, the resource utilization phase from the lookuptable.

Example 22 includes the subject matter of any of Examples 14-21, andwherein the resource utilization phase is a first resource utilizationphase and the workload fingerprint comprises a residency matrixindicative of a time duration that a workload remains in a givenresource utilization phase and further comprises a transitionprobability matrix indicative of a likelihood that the workloadtransitions to a second resource utilization phase.

Example 23 includes the subject matter of any of Examples 14-22, andwherein updating the workload fingerprint comprises recalculating theresidency matrix and the transition probability matrix based on thedetermined resource utilization phase.

Example 24 includes the subject matter of any of Examples 14-23, andwherein obtaining the telemetry data comprises writing a value to aregister indicative of an instruction to start a counter in theperformance monitor unit; and causing, in response to the write of thevalue to the register, the performance monitor unit to start thecounter.

Example 25 includes the subject matter of any of Examples 14-24, andfurther including writing, by the sled, a second value to the registerindicative of an instruction to pause the counter in the performancemonitor unit.

Example 26 includes the subject matter of any of Examples 14-25, andwherein obtaining the telemetry data comprises retrieving one or more ofa number of cache misses per thousand instructions, a number of cyclesper instruction, or cache occupancy data.

Example 27 includes one or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a sled to perform the method of any of Examples14-26.

Example 28 includes a sled comprising means for performing the method ofany of Examples 14-26.

Example 29 includes a sled comprising a compute engine to perform themethod of any of Examples 14-26.

Example 30 includes a sled, comprising a performance monitor unit; andphase detector circuitry to obtain telemetry data from the performancemonitor unit, wherein the performance monitor unit is to producetelemetry data indicative of resource utilization and workloadperformance by the sled as one or more workloads are executed,determine, from a lookup table indicative of a plurality of resourceutilization phases, a resource utilization phase based on the obtainedtelemetry data, update a workload fingerprint based on the determinedresource utilization phase, and output the workload fingerprint.

Example 31 includes the subject matter of Example 30, and wherein tooutput the workload fingerprint comprises to output the workloadfingerprint to an area of memory in the sled reserved by the performancemonitor unit.

Example 32 includes the subject matter of any of Examples 30 and 31, andwherein the phase detector circuitry is further to retrieve the workloadfingerprint from the area of memory; evaluate the workload fingerprintrelative to policy data; the sled further comprising remediation enginecircuitry to determine a remedial action to perform in response to theevaluation; and perform the remedial action.

Example 33 includes the subject matter of any of Examples 30-32, andwherein the phase detector circuitry is further to initialize the lookuptable with the plurality of resource utilization phases.

Example 34 includes the subject matter of any of Examples 30-33, andwherein to initialize the lookup table with the plurality of resourceutilization phases comprises to execute the one or more workloads withtraining data as input; generate a resource utilization phase modelbased on telemetry data collected from the execution of the one or moreworkloads with the training data as input; and populate the lookup tablewith discretized telemetry data determined based on the resourceutilization phase model.

Example 35 includes the subject matter of any of Examples 30-34, andwherein the phase detector circuitry is further to program theperformance monitor unit to monitor the telemetry data at boot time ofthe sled.

Example 36 includes the subject matter of any of Examples 30-35, andwherein to program the performance monitor unit comprises to write avalue to a register indicative of an instruction to configure, in theperformance monitor unit, one or more events to monitor during theexecution of the one or more workloads.

Example 37 includes the subject matter of any of Examples 30-36, andwherein to determine the resource utilization phase based on theobtained telemetry data comprises to discretize the telemetry data;query the lookup table using the discretized telemetry data; andreceive, in response to the query, the resource utilization phase fromthe lookup table.

Example 38 includes the subject matter of any of Examples 30-37, andwherein the resource utilization phase is a first resource utilizationphase and the workload fingerprint comprises a residency matrixindicative of a time duration that a workload remains in a givenresource utilization phase and further comprises a transitionprobability matrix indicative of a likelihood that the workloadtransitions to a second resource utilization phase.

Example 39 includes the subject matter of any of Examples 30-38, andwherein to update the workload fingerprint comprises to recalculate theresidency matrix and the transition probability matrix based on thedetermined resource utilization phase.

Example 40 includes the subject matter of any of Examples 30-39, andwherein to obtain the telemetry data comprises to write a value to aregister indicative of an instruction to start a counter in theperformance monitor unit; and cause, in response to the write of thevalue to the register, the performance monitor unit to start thecounter.

Example 41 includes the subject matter of any of Examples 30-40, andwherein the phase detector circuitry is further to write a second valueto the register indicative of an instruction to pause the counter in theperformance monitor unit.

Example 42 includes the subject matter of any of Examples 30-41, andwherein to obtain the telemetry data comprises to retrieve one or moreof a number of cache misses per thousand instructions, a number ofcycles per instruction, or cache occupancy data.

Example 43 includes a sled, comprising circuitry for obtaining telemetrydata from a performance monitor unit in the sled, wherein theperformance monitor unit is to produce telemetry data indicative ofresource utilization and workload performance by the sled as one or moreworkloads are executed, means for determining, from a lookup tableindicative of a plurality of resource utilization phases, a resourceutilization phase based on the obtained telemetry data, means forupdating a workload fingerprint based on the determined resourceutilization phase, and circuitry for outputting the workloadfingerprint.

Example 44 includes the subject matter of Example 43, and wherein thecircuitry for outputting the workload fingerprint comprises circuitryfor outputting the workload fingerprint to an area of memory in the sledreserved by the performance monitor unit.

Example 45 includes the subject matter of any of Examples 43 and 44, andfurther including circuitry for retrieving the workload fingerprint fromthe area of memory; means for evaluating the workload fingerprintrelative to policy data; means for determining a remedial action toperform in response to the evaluation; and means for performing theremedial action.

Example 46 includes the subject matter of any of Examples 43-45, andfurther including circuitry for initializing the lookup table with theplurality of resource utilization phases.

Example 47 includes the subject matter of any of Examples 43-46, andwherein the circuitry for initializing the lookup table with theplurality of resource utilization phases comprises circuitry forexecuting the one or more workloads with training data as input;circuitry for generating a resource utilization phase model based ontelemetry data collected from the execution of the one or more workloadswith the training data as input; and circuitry for populating the lookuptable with discretized telemetry data determined based on the resourceutilization phase model.

Example 48 includes the subject matter of any of Examples 43-47, andfurther including means for programming the performance monitor unit tomonitor the telemetry data at boot time of the sled.

Example 49 includes the subject matter of any of Examples 43-48, andwherein the means for programming the performance monitor unit comprisescircuitry for writing a value to a register indicative of an instructionto configure, in the performance monitor unit, one or more events tomonitor during the execution of the one or more workloads.

Example 50 includes the subject matter of any of Examples 43-49, andwherein the means for determining the resource utilization phase basedon the obtained telemetry data comprises circuitry for discretizing thetelemetry data; circuitry for querying the lookup table using thediscretized telemetry data; and circuitry for receiving, in response tothe query, the resource utilization phase from the lookup table.

Example 51 includes the subject matter of any of Examples 43-50, andwherein the resource utilization phase is a first resource utilizationphase and the workload fingerprint comprises a residency matrixindicative of a time duration that a workload remains in a givenresource utilization phase further comprises a transition probabilitymatrix indicative of a likelihood that the workload transitions to asecond resource utilization phase.

Example 52 includes the subject matter of any of Examples 43-51, andwherein the means for updating the workload fingerprint comprisescircuitry for recalculating the residency matrix and the transitionprobability matrix based on the determined resource utilization phase.

Example 53 includes the subject matter of any of Examples 43-52, andwherein the circuitry for obtaining the telemetry data comprisescircuitry for writing a value to a register indicative of an instructionto start a counter in the performance monitor unit; and circuitry forcausing, in response to the write of the value to the register, theperformance monitor unit to start the counter.

Example 54 includes the subject matter of any of Examples 43-53, andwherein the phase detector circuitry is further to write a second valueto the register indicative of an instruction to pause the counter in theperformance monitor unit.

Example 55 includes the subject matter of any of Examples 43-54, andwherein to obtain the telemetry data comprises to retrieve one or moreof a number of cache misses per thousand instructions, a number ofcycles per instruction, or cache occupancy data.

1. A sled, comprising: communication circuitry; a compute enginecomprising a performance monitor unit, wherein the compute engine is to(i) obtain telemetry data from the performance monitor unit, wherein theperformance monitor unit is to produce telemetry data indicative ofresource utilization and workload performance by the sled as one or moreworkloads are executed, (ii) determine, from a lookup table indicativeof a plurality of resource utilization phases, a resource utilizationphase based on the obtained telemetry data, (iii) update a workloadfingerprint based on the determined resource utilization phase, and (iv)output the workload fingerprint.
 2. The sled of claim 1, wherein tooutput the workload fingerprint comprises to output the workloadfingerprint to an area of memory in the sled reserved by the performancemonitor unit.
 3. The sled of claim 2, wherein the compute engine isfurther to: retrieve the workload fingerprint from the area of memory;evaluate the workload fingerprint relative to policy data; determine aremedial action to perform in response to the evaluation; and performthe remedial action.
 4. The sled of claim 1, wherein the compute engineis further to initialize the lookup table with the plurality of resourceutilization phases.
 5. The sled of claim 4, wherein to initialize thelookup table with the plurality of resource utilization phases comprisesto: execute the one or more workloads with training data as input;generate a resource utilization phase model based on telemetry datacollected from the execution of the one or more workloads with thetraining data as input; and populate the lookup table with discretizedtelemetry data determined based on the resource utilization phase model.6. The sled of claim 1, wherein the compute engine is further to programthe performance monitor unit to monitor the telemetry data at boot timeof the sled.
 7. The sled of claim 6, wherein to program the performancemonitor unit comprises to write a value to a register indicative of aninstruction to configure, in the performance monitor unit, one or moreevents to monitor during the execution of the one or more workloads. 8.The sled of claim 1, wherein to determine the resource utilization phasebased on the obtained telemetry data comprises to: discretize thetelemetry data; query the lookup table using the discretized telemetrydata; and receive, in response to the query, the resource utilizationphase from the lookup table.
 9. The sled of claim 1, wherein theresource utilization phase is a first resource utilization phase and theworkload fingerprint comprises a residency matrix indicative of a timeduration that a workload remains in a given resource utilization phaseand further comprises a transition probability matrix indicative of alikelihood that the workload transitions to a second resourceutilization phase.
 10. The sled of claim 9, wherein to update theworkload fingerprint comprises to recalculate the residency matrix andthe transition probability matrix based on the determined resourceutilization phase.
 11. The sled of claim 1, wherein to obtain thetelemetry data comprises to: write a value to a register indicative ofan instruction to start a counter in the performance monitor unit; andcause, in response to the write of the value to the register, theperformance monitor unit to start the counter.
 12. The sled of claim 11,wherein the compute engine is further to write a second value to theregister indicative of an instruction to pause the counter in theperformance monitor unit.
 13. The sled of claim 1, wherein to obtain thetelemetry data comprises to retrieve one or more of a number of cachemisses per thousand instructions, a number of cycles per instruction, orcache occupancy data.
 14. One or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a sled to: obtain telemetry data produced by aperformance monitor unit of the sled, wherein the telemetry data isindicative of resource utilization and workload performance by the sledas one or more workloads are executed; determine from a lookup tableindicative of a plurality of resource utilization phases, a resourceutilization phase based on the obtained telemetry data; update aworkload fingerprint based on the determined resource utilization phase;and output the workload fingerprint.
 15. The one or moremachine-readable storage media of claim 14, wherein to output theworkload fingerprint comprises to output the workload fingerprint to anarea of memory in the sled reserved by the performance monitor unit. 16.The one or more machine-readable storage media of claim 15, wherein theplurality of instructions further cause the sled to: retrieve theworkload fingerprint from the area of memory; evaluate the workloadfingerprint relative to policy data; determine a remedial action toperform in response to the evaluation; and perform the remedial action.17. The one or more machine-readable storage media of claim 14, whereinthe plurality of instructions further cause the sled to initialize thelookup table with the plurality of resource utilization phases.
 18. Theone or more machine-readable storage media of claim 17, wherein toinitialize the lookup table with the plurality of resource utilizationphases comprises to: execute the one or more workloads with trainingdata as input; generate a resource utilization phase model based ontelemetry data collected from the execution of the one or more workloadswith the training data as input; and populate the lookup table withdiscretized telemetry data determined based on the resource utilizationphase model.
 19. The one or more machine-readable storage media of claim14, wherein the plurality of instructions further cause the sled toprogram the performance monitor unit to monitor the telemetry data atboot time of the sled.
 20. The one or more machine-readable storagemedia of claim 19, wherein to program the performance monitor unitcomprises to write a value to a register indicative of an instruction toconfigure, in the performance monitor unit, one or more events tomonitor during the execution of the one or more workloads.
 21. The oneor more machine-readable storage media of claim 14, wherein to determinethe resource utilization phase based on the obtained telemetry datacomprises to: discretize the telemetry data; query the lookup tableusing the discretized telemetry data; and receive, in response to thequery, the resource utilization phase from the lookup table.
 22. The oneor more machine-readable storage media of claim 14, wherein the resourceutilization phase is a first resource utilization phase and the workloadfingerprint comprises a residency matrix indicative of a time durationthat a workload remains in a given resource utilization phase andfurther comprises a transition probability matrix indicative of alikelihood that the workload transitions to a second resourceutilization phase.
 23. The one or more machine-readable storage media ofclaim 22, wherein to update the workload fingerprint comprisesrecalculating the residency matrix and the transition probability matrixbased on the determined resource utilization phase.
 24. A sled,comprising: circuitry for obtaining telemetry data from a performancemonitor unit of the sled, wherein the performance monitor unit is toproduce telemetry data indicative of resource utilization and workloadperformance by the sled as one or more workloads are executed; means fordetermining, from a lookup table indicative of a plurality of resourceutilization phases, a resource utilization phase based on the obtainedtelemetry data; means for updating a workload fingerprint based on thedetermined resource utilization phase; and circuitry for outputting theworkload fingerprint.
 25. A method, comprising: obtaining, by a sledthat includes a performance monitor unit, telemetry data produced by theperformance monitor unit, wherein the telemetry data is indicative ofresource utilization and workload performance by the sled as one or moreworkloads are executed; determining, by the sled and from a lookup tableindicative of a plurality of resource utilization phases, a resourceutilization phase based on the obtained telemetry data; updating, by thesled, a workload fingerprint based on the determined resourceutilization phase; and outputting, by the sled, the workloadfingerprint.
 26. The method of claim 25, wherein outputting the workloadfingerprint comprises outputting the workload fingerprint to an area ofmemory in the sled reserved by the performance monitor unit.
 27. Themethod of claim 26, further comprising: retrieving, by the sled, theworkload fingerprint from the area of memory; evaluating, by the sled,the workload fingerprint relative to policy data; determining, by thesled, a remedial action to perform in response to the evaluation; andperforming, by the sled, the remedial action.
 28. The method of claim25, further comprising initializing, by the sled, the lookup table withthe plurality of resource utilization phases.